As well-known to those skilled in the art, DDR (Double Data Rate), in which data are input and output in synchronization with rising and falling edges of a clock signal at the data I/O operation, operates in a burst mode in order to execute consecutive read or write operations.
In the burst mode, the burst length of BL4 or BL8 is typically used. Here, BL4 is set up to four (4) in the burst length so that 4-bit data are input and output according to one command signal. On the other hand, in the burst length of BL8, 8-bit data are input and output according to one command signal.
Meanwhile, a prefetch technique is used in the DDR. Typically, 2-bit prefetch is employed in the DDR so that two bits of the data are consecutively output and 4-bit prefetch is employed in the DDR2 so that four bits of the data are consecutively output.
FIG. 1 is a detailed circuit diagram illustrating a conventional burst length control circuit which is used in the DDR2 in which a 4-bit prefetch.
As shown in FIG. 1, the conventional burst length control circuit receives a burst signal SBL4 for setting up the burst length, and a read signal IRDP which is activated by an external read command, and a write signal IWTP which is activated by an external write command, and then generates a buffer control signal FYBST and a column control signal IYBST. Here, the buffer control signal FYBST is a signal to control an enable section of a data I/O buffer and the column control signal IYBST is a signal to produce a column select signal YI for data transfer between a data I/O line and a sense amplifier.
Hereinafter, the burst length control circuit of FIG. 1 will be described divides into burst lengths of BL4 and BL8.
First, in the burst length of BL4, since the burst signal SBL4 is at a high voltage level, a PMOS transistor P10 is turned on such that a pull-up operation is carried out at a node nd10. A signal on the node nd10 is transferred through transfer gates T10, T11 and T12, that are selectively turned on in response to a clock signal BCKB, so that both the buffer control signal FYBST and the column control signal IYBST are set up to a low level. In the case where both the buffer control signal FYBST and the column control signal IYBST are set up to a low level, the data I/O buffer is maintained in a disable state and the column select signal YI is not produced. Basically, in the case of the DDR2 in which 4-bit prefetch is applied to, 4-bit data are output through the data I/O buffer, regardless of the control of the buffer control signal FYBST and the column control signal IYBST.
Next, in the burst length of BL8, the burst signal SBL4 is at a low voltage level. At this time, since the node nd10 is initialized at a high level by a reset signal RST and a node nd12 is also initialized at a high level by the transfer gate T10 which is turned on in response to the clock signal BCKB, a high level signal is output by a NAND gate ND11. When a NMOS transistor N10 is turned on in response to both the burst signal SBL4 of a low level and the high level signal of the NAND gate ND11 and a NMOS transistor N11 is turned on in response to write signal IWTP or a NMOS transistor N12 is turned on in response to read signal IRDP, the node nd10 is pull-down driven to a low level. An output signal of the node nd10 is transferred by the transfer gates T10, T11 and T12, which are selectively turned on in response to the clock signal BCKB, so that the buffer control signal FYBST and the column control signal IYBST transit to a high level.
At this time, the enable section of the buffer control signal FYBST and the column control signal IYBST is determined by a transition section of the voltage level on the node nd12. In more detail, the signal on the node nd10, which is pull-down driven to a low level by the turned-on NMOS transistor N10, is transferred to the node nd12 by the transfer gate T10 which is turned on in response to a falling edge of the clock signal BCKB. If the low level signal on the node nd12 is input at a rising edge of the clock signal BCKB, the NAND gate ND11 outputs a low level signal and the node nd10 is pull-up driven to a high level by the turned-on PMOS transistor P10. The high level signal on the node nd10 is transferred to the node nd12 by the transfer gate T10 which is turned on in response to a falling edge of the clock signal BCKB so that the node nd12 transits to a high level. As mentioned above, since the node nd12 is maintained at a low level during one period (1tCK) of the clock signal BCKB, the enable section of the buffer control signal FYBST and the column control signal IYBST is also set up to the one period (1tCK) of the clock signal BCKB.
If the column control signal IYBST is enabled at a high level during one period (1tCK) of the clock signal BCKB, the column select signal YI is generated to consecutively input and output the 4-bit data and, if the buffer control signal FYBST is enabled at a high level during one period (1tCK) of the clock signal BCKB, the data I/O buffer is enabled to consecutively input and output the 4-bit data. As mentioned above, basically, in the case of the DDR2 in which 4-bit prefetch is applied to, since 4-bit data are output through the data I/O buffer, regardless of the control of the buffer control signal FYBST and the column control signal IYBST, the 8-bit data are consecutively input and output in the burst length of BL8.
As illustrated above, in the conventional burst control circuit of DDR2, the burst lengths of BL4 and BL8 are controlled by the burst signal SBL4. However, the burst length of BL16 is not supported by it.